During a gate fabricating process of CMOS technology for 32 nm technology node or smaller, in order to optimize the performance of the semiconductor material fabricated, a semiconductor device fabricating method employs a gate-last processing technology and a high dielectric constant gate insulating dielectric (core gate dielectric) forming technology. This semiconductor device fabricating method which combines a gate-last processing technology and a high dielectric constant gate insulating dielectric (core gate dielectric) forming technology is capable of reducing the thickness of the oxide layer (EOT/Tinv), and thereby, improving technical ductility of the material. Moreover, this semiconductor device fabricating method which combines the gate-last process and a high dielectric constant gate insulating dielectric (core gate dielectric) can also improve the ability of the semiconductor material fabricated in withstanding a heat treatment process for a lightly doped drain region and source region.
FIGS. 1a to 1e illustrate a semiconductor device fabricating method which combines a gate-last processing technology and a high dielectric constant gate insulating dielectric (core gate dielectric) forming technology.
As shown in FIG. 1a, a shallow trench isolation region STI 11′ (STI: Shallow Trench Isolation) is formed in a surface of a substrate 1′. An oxide layer is deposited on the surface of the substrate, but not on the surface of the shallow trench isolation region 11′. A layer of dummy gate material is deposited on the oxide layer. A first photoresist layer is formed on an upper surface of the dummy gate material layer where a dummy gate structure is to be formed. The surface area of the dummy gate material layer that is not covered by the photoresist layer is removed to obtain the dummy gate structure. The dummy gate structure comprises an input/output (I/O) dummy gate 31′ and a core dummy gate 33′. An oxide layer 2′ located below the dummy gate material layer is further etched to form an input/output (I/O) oxide layer 21′ located between the I/O dummy gate 31′ and the substrate l′, and a core oxide layer 23′ located between the core dummy gate 33′ and the substrate 1′.
An LDD ion implant is performed in the substrate to form LDD doped regions on opposite sides of the I/O dummy gate 31′ and the core dummy gate 33′, a sidewall spacer structure is formed on the sidewall of the I/O dummy gate 31′ and the core dummy gate 33′, respectively. Thereafter, an ion implant is performed in the substrate on the two sides of the sidewall layer of the I/O dummy gate 31′ and of the core dummy gate 33′ to form a source region and a drain region on opposite sides of the I/O dummy gate 31′ and the core dummy gate 33′.
An NiSi layer 4 is deposited on the surface of the substrate on which the I/O dummy gate 31′, the core dummy gate 33′ and the shallow trench isolation region 11′ are not formed. An etch barrier layer 5′ is formed on the side surface of the sidewall layer surrounding the I/O dummy gate 31′ and the core dummy gate 33′. The etch barrier layer 5′ extends along the sidewall of the I/O dummy gate 31′ and of the core dummy gate 33′, extends upwards to be flush with the upper surface of the dummy gate, and extends downwards continuously and covers the NiSi layer 4′ and the shallow trench isolation region 11′.
As shown in FIG. 1b, a second photoresist layer 71′ is formed on the upper surface of the I/O dummy gate 31′, the upper surface of the etch barrier layer 5′ and the dielectric layer 6′ surrounding the I/O dummy gate 31′. The core dummy gate 33′ and the core oxide layer 23′ are removed by etching, and a core gate groove 37′ is formed at a location corresponding to the core dummy gate 33′. The second photoresist layer 71′ on the upper surface of and surrounding the I/O dummy gate 31′ is then removed.
As shown in FIG. 1c, a core gate dielectric layer 8′ is deposited on the substrate 1′ in the core gate groove 37′.
As shown in FIG. 1d, a third photoresist layer 72′ is formed in the core gate groove 37′ where the core gate dielectric layer 8′ is formed, on the upper surface of the etch barrier layer 5′ surrounding the core gate groove 37′, and the upper surface of the dielectric layer 6′, the I/O dummy gate 31′ is removed by etching, and an input/output (I/O) gate groove 35′ is formed at a location corresponding to the I/O dummy gate 31′. The third photoresist layer 72′ within and surrounding the core gate groove 37′ is then removed.
As shown in FIG. 1e, a layer of a material having a high dielectric constant and a metal gate 9′ located on the layer with the material having a high dielectric constant are formed in the I/O gate groove 35′ and the core gate groove 37′.
In the above semiconductor device fabricating method which combines a gate-last processing technology and a core gate dielectric forming technology, in order to avoid affecting the I/O oxide layer 21′ when etching the core oxide layer 23′, the I/O dummy gate 31′ must first be shielded. Then the core dummy gate 33′ is removed, after the removal of the core dummy gate, the core oxide layer 23′ is removed to form the core gate groove 37′. Thereafter, the core gate dielectric layer 8′ is formed on the substrate 1′ in the core gate groove 37′. After the completion of the deposition of the core gate dielectric layer 8′, the I/O dummy gate 31′ is removed by shielding the core gate groove 37′ to form an I/O gate groove with the I/O oxide layer retained.
Although this conventional fabricating method can avoid the I/O oxide layer from being affected when etching the core oxide layer, this method employs difficult and complicated technology steps to achieve that and hence has the drawback of a high manufacturing cost, which is not advantageous for large-scale fabrication.